module slave_mem(
    input clk,
    input rst_n,

    input mem_valid_master,
    output mem_ready_master,
    input [31:0] mem_addr_master,
    input [3:0] mem_wstrb_master,
    input [31:0] mem_wdata_master,
    output [31:0] mem_rdata_master,

    output mem_valid_slave0,
    input mem_ready_slave0,
    output [31:0] mem_addr_slave0,
    output [3:0] mem_wstrb_slave0,
    output [31:0] mem_wdata_slave0,
    input [31:0] mem_rdata_slave0,

    output mem_valid_slave1,
    input mem_ready_slave1,
    output [31:0] mem_addr_slave1,
    output [3:0] mem_wstrb_slave1,
    output [31:0] mem_wdata_slave1,
    input [31:0] mem_rdata_slave1,

    output mem_valid_slave2,
    input mem_ready_slave2,
    output [31:0] mem_addr_slave2,
    output [3:0] mem_wstrb_slave2,
    output [31:0] mem_wdata_slave2,
    input [31:0] mem_rdata_slave2
);
assign mem_ready_master = (mem_addr_master[31:24] == 'h00) ? mem_ready_slave0 :
                            (mem_addr_master[31:24] == 'h01) ? mem_ready_slave1 : 
                            (mem_addr_master[31:24] == 'h02) ? mem_ready_slave2 : 'b0;
assign mem_rdata_master = (mem_addr_master[31:24] == 'h00) ? mem_rdata_slave0 :
                            (mem_addr_master[31:24] == 'h01) ? mem_rdata_slave1 :
                            (mem_addr_master[31:24] == 'h02) ? mem_rdata_slave2 :'h0000_0000_0000_0000;

assign mem_valid_slave0 = (mem_addr_master[31:24] == 'h00) ? mem_valid_master : 'b0;
assign mem_valid_slave1 = (mem_addr_master[31:24] == 'h01) ? mem_valid_master : 'b0;
assign mem_valid_slave2 = (mem_addr_master[31:24] == 'h02) ? mem_valid_master : 'b0;

assign mem_addr_slave0 = (mem_addr_master[31:24] == 'h00) ? mem_addr_master : 'h0000_0000_0000_0000;
assign mem_addr_slave1 = (mem_addr_master[31:24] == 'h01) ? mem_addr_master : 'h0000_0000_0000_0000;
assign mem_addr_slave2 = (mem_addr_master[31:24] == 'h02) ? mem_addr_master : 'h0000_0000_0000_0000;

assign mem_wstrb_slave0 = (mem_addr_master[31:24] == 'h00) ? mem_wstrb_master : 'b0000;
assign mem_wstrb_slave1 = (mem_addr_master[31:24] == 'h01) ? mem_wstrb_master : 'b0000;
assign mem_wstrb_slave2 = (mem_addr_master[31:24] == 'h02) ? mem_wstrb_master : 'b0000;

assign mem_wdata_slave0 = (mem_addr_master[31:24] == 'h00) ? mem_wdata_master : 'h0000_0000_0000_0000;
assign mem_wdata_slave1 = (mem_addr_master[31:24] == 'h01) ? mem_wdata_master : 'h0000_0000_0000_0000;
assign mem_wdata_slave2 = (mem_addr_master[31:24] == 'h02) ? mem_wdata_master : 'h0000_0000_0000_0000;

endmodule